Stego on FPGA: An IWT Approach

Table 2

IWT stego processor compilation report.

Family	Cyclone II
Device	EP2C35F672C6
Timing models	Final
Met timing requirements	Yes
Total logic elements	11.222/33.216 (34%)
Total combinational functions	8.792/33.216 (26%)
Dedicated logic registers	7.412/33.216 (22%)
Total registers	7412
Total pins	44/475 (9%)
Total virtual pins	0
Total memory bits	0/483.840 (0%)
Embedded multiplier 9-bit elements	2/70 (3%)
Total PLLs	0/4 (0%)