Continuous-Time ΣΔ ADC with Implicit Variable Gain Amplifier for CMOS Image Sensor

Table 1

CIS-purpose ΣΔ ADC figure-of-merit comparison.

Specification	This work CTSD	JSSC 09 DTSD [7]	JSSC 09 DTSD [7]	JSSC 11 DTSD [5]
Power com. 𝜇W	58.5 (ANA) + 5 (DIG)	36 𝜇W (ANA)	5.6 𝜇W (ANA)	40 (ANA) + 3.5 (DIG)
Core area  𝜇m^2	3 k (ANA) + 3.5 k (DIG)	715 k (ANA) + N/A (DIG)	3 k (ANA) + N/A (DIG)	1.35 k (ANA) + 1.35 k (DIG)
Order	2	3	2	2
Peak SNDR	66.21 dB	81 dB	63 dB	—
Peak SNR	72 dB	84 dB	72 dB	66 dB
ENOB	10.71 bits	13.16 bits	10.17 bits	—
Dynamic range	74 dB at  𝐺=0	85 dB	76 dB	75 dB
	86 dB at 𝐺=7
Bandwidth	250 KHz	20 KHz	8 KHz	220 KHz
Process	0.18 𝜇m		0.35 𝜇m	0.13 𝜇m
FOM1; fJ/step	25 at 𝐺=0	51	55	17
	6.4 at 𝐺=7
FOM2  𝜇m^2/Hz·step	2.6 at 𝐺=0	1000	30	1.1
	0.7 at 𝐺=7