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The Scientific World Journal
Volume 2014, Article ID 258068, 8 pages
http://dx.doi.org/10.1155/2014/258068
Research Article

A High-Speed and Low-Offset Dynamic Latch Comparator

1Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia
2Mimos Berhad, 57000 Kuala Lumpur, Malaysia

Received 15 March 2014; Revised 27 May 2014; Accepted 10 June 2014; Published 9 July 2014

Academic Editor: Ramesh Pokharel

Copyright © 2014 Labonnah Farzana Rahman et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [6 citations]

The following is the list of published articles that have cited the current article.

  • Labonnah F. Rahman, Mamun B. I. Reaz, Mohammad A. S. Bhuiyan, and Md. T. I. Badal, “Design of a row decoder for RFID transponder EEPROM,” 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES), pp. 155–158, . View at Publisher · View at Google Scholar
  • Alak Majumder, Monalisa Das, Bipasha Nath, Abir J Mondal, and Bidyut K Bhattacharyya, “Design of low noise high speed novel dynamic Analog Comparator in 65nm technology,” 2016 26th International Conference Radioelektronika (RADIOELEKTRONIKA), pp. 115–120, . View at Publisher · View at Google Scholar
  • Dinanath N. Donadkar, and Sheetal U. Bhandari, “Review on comparator design for high speed ADCs,” Proceedings - 1st International Conference on Computing, Communication, Control and Automation, ICCUBEA 2015, pp. 974–978, 2015. View at Publisher · View at Google Scholar
  • M. Cho, H. Kim, K.T. Lim, and G. Cho, “Development of a Position Decoding ASIC for SPECT using Silicon Photomultiplier,” Journal of Instrumentation, vol. 11, no. 01, pp. C01065–C01065, 2016. View at Publisher · View at Google Scholar
  • Alak Majumder, Abir J. Mondal, and Bidyut K. Bhattacharyya, “A 65 nm Design of 0.6 V/8.98 μw process-voltage-Temperature aware dynamic analog comparator for high speed data reconstruction applications,” Journal of Low Power Electronics, vol. 13, no. 3, pp. 511–519, 2017. View at Publisher · View at Google Scholar
  • Avaneesh K. Dubey, and R.K. Nagaria, “Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load,” Microelectronics Journal, vol. 78, pp. 1–10, 2018. View at Publisher · View at Google Scholar