Research Article
A High-Speed and Low-Offset Dynamic Latch Comparator
Table 2
Comparison study of the proposed latch comparator performance.
| References | [7] | [8] | [9] | [10] | [11] | [12] | This work | Year | 2009 | 2010 | 2010 | 2011 | 2012 | 2013 |
| Technology (m-CMOS) | 0.35 | 0.5 | 0.18 | 0.18 | 0.9 | 0.65 | 0.18 | Supply voltage (V) | 1.2 | ±1.5 | 1.8 | 1 | 1 | 1 | 1.8 | Power (W) | 8.4 | — | 225 | 63.5 | 240 | 157 | 158.5 | Sampling rate (MHz) | 20 | — | 30 | 20 | 50 | 50 | 50 | Resolution (bits) | 8 | — | 8 | 12 | 6 | 7 | 8 | Propagations delay (nS) | — | 932a | — | 26a | — | — | 4.2 | Offset voltage (mV) | 3 | 24.2 | — | 0.0476 | — | — | 3.44 | FOM (fj/conv) | 1.64 | — | 29.2 | 0.77 | 150 | 28 | 0.7 |
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Measured value.
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