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The Scientific World Journal
Volume 2014, Article ID 286084, 12 pages
Research Article

Characterizing the Effects of Intermittent Faults on a Processor for Dependability Enhancement Strategy

1Multicore Research Institute, High Performance CPU Center, Tsinghua University, Building F.I.T, Beijing 100084, China
2School of Computer Science, Harbin Institute of Technology, No. 155 Fanrong Street, Nangang District, Harbin 150001, China
3School of Computer and Communication Engineering, University of Science and Technology Beijing, No. 30 Xueyuan Road, Haidian District, Beijing 100083, China

Received 31 August 2013; Accepted 17 March 2014; Published 28 April 2014

Academic Editors: J. Shu and F. Yu

Copyright © 2014 Chao(Saul) Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


As semiconductor technology scales into the nanometer regime, intermittent faults have become an increasing threat. This paper focuses on the effects of intermittent faults on NET versus REG on one hand and the implications for dependability strategy on the other. First, the vulnerability characteristics of representative units in OpenSPARC T2 are revealed, and in particular, the highly sensitive modules are identified. Second, an arch-level dependability enhancement strategy is proposed, showing that events such as core/strand running status and core-memory interface events can be candidates of detectable symptoms. A simple watchdog can be deployed to detect application running status (IEXE event). Then SDC (silent data corruption) rate is evaluated demonstrating its potential. Third and last, the effects of traditional protection schemes in the target CMT to intermittent faults are quantitatively studied on behalf of the contribution of each trap type, demonstrating the necessity of taking this factor into account for the strategy.