The Scientific World Journal
Volume 2014, Article ID 405893, 5 pages
http://dx.doi.org/10.1155/2014/405893
Low Power Adder Based Digital Filter for QRS Detector
1Department of ECE, Hindusthan College of Engineering and Technology, Coimbatore, India
2Department of CSE, P.A. College of Engineering and Technology, Pollachi, India
3P.A. College of Engineering and Technology, Pollachi, India
Received 5 March 2014; Revised 12 April 2014; Accepted 13 April 2014; Published 6 May 2014
Academic Editor: Christina Chrysohoou
Copyright © 2014 L. Murali et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.