Table of Contents Author Guidelines Submit a Manuscript
The Scientific World Journal
Volume 2014, Article ID 405893, 5 pages
Research Article

Low Power Adder Based Digital Filter for QRS Detector

1Department of ECE, Hindusthan College of Engineering and Technology, Coimbatore, India
2Department of CSE, P.A. College of Engineering and Technology, Pollachi, India
3P.A. College of Engineering and Technology, Pollachi, India

Received 5 March 2014; Revised 12 April 2014; Accepted 13 April 2014; Published 6 May 2014

Academic Editor: Christina Chrysohoou

Copyright © 2014 L. Murali et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. S. Gupta, Low power VLSI design of a FIR filter using dual edge triggered clocking strategy [M.S. thesis], NIT, Rourkela, India, 2008.
  2. S. Izumi, M. Nakano, K. Yamashita et al., “Low-power hardware implementation of noise tolerant heart rate extractor for a wearable monitoring system,” in Proceedings of the IEEE 13th International Conference on Bioinformatics and Bioengineering (BIBE '13), pp. 1–4, Institute of Electrical and Electronics Engineers IEEE, 2013.
  3. Database on Body Sensor Network—An Introduction, Imperial College, London, UK, 2010,
  4. X. Liu, J. Zhou, X. Liao et al., “Ultra-low-energy near-threshold biomedical signal processor for versatile wireless health monitoring,” in Proceedings of the 2012 IEEE Asian Solid-State Circuits Conference, pp. 12–14, Kobe, Japan, November 2012.
  5. M. Simon, “Intra-body communication for biomedical sensor networks,” Diss. ETH 17323, ETH, Zurich, Switzerland, 2007. View at Google Scholar
  6. S. C. Huang, Y. L. Lai, S. H. Lin et al., “A ±6ms-accuracy, 0.68 mm2, and 2.21 μW QRS detection ASIC,” VLSI Design, vol. 2012, Article ID 809393, 13 pages, 2012. View at Publisher · View at Google Scholar
  7. S. Yang, W. Wolf, N. Vijaykrishnan, Y. Xie, and W. Wang, “Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits,” in Proceedings of the 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems, pp. 165–170, IEEE, January 2005. View at Scopus
  8. U. Chandra Mohan, “Low power area efficient digital counters,” in Proceedings of the 7th VLSI Design and Test Workshops (VDAT '03), August 2003.