Low Power Adder Based Digital Filter for QRS Detector

Table 1

Results of variable bit widths adder architecture using TSMC standard full adder cell and proposed full adder cell.

Bit widths	Parameter	Existing	Proposed	% gain
4	Area	40.32	48.96	−21.42
	Timing	0.35	0.57	−62.85
	Dp	9.35	7.47	20.10
	Lp	0.61	0.42	31.05
8	Area	80.63	97.92	−21.44
	Timing	0.62	1.06	−70.96
	Dp	19.38	15.49	20.07
	Lp	1.23	0.84	31.19
16	Area	161.27	195.84	−21.43
	Timing	1.17	2.04	−74.35
	Dp	39.81	31.71	20.34
	Lp	2.46	1.69	31.15
32	Area	322.55	391.68	−21.43
	Timing	2.27	3.99	−75.77
	Dp	80.59	64.18	20.36
	Lp	4.92	3.39	31.14