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The Scientific World Journal
Volume 2014, Article ID 453675, 14 pages
Research Article

A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

1Department of Electrical Engineering, Delhi Technological University, Room No. FW1-SF1, EED, DTU, New Delhi 110042, India
2Division of ECE, Netaji Subhas Institute of Technology (NSIT), University of Delhi, Sector 3, Dwarka, New Delhi 110078, India

Received 28 August 2013; Accepted 13 October 2013; Published 27 February 2014

Academic Editors: L. Donetti, E. Tlelo-Cuautle, and F. Yuan

Copyright © 2014 Kunwar Singh et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Kavitha, Shiyamala, and Nagarajan, “Efficient timing element design featuring low power VLSI applications,” International Journal of Engineering and Technology, vol. 8, no. 4, pp. 1696–1705, 2016. View at Publisher · View at Google Scholar
  • Kunwar Singh, Satish Chandra Tiwari, and Maneesha Gupta, “State-of-the-Art Master Slave Flip-Flop Designs for Low Power VLSI Systems,” Design and Modeling of Low Power VLSI Systems, pp. 166–198, 2016. View at Publisher · View at Google Scholar
  • Nezam Rohbani, and Seyed-Ghassem Miremadi, “A Low-Overhead Integrated Aging and SEU Sensor,” IEEE Transactions on Device and Materials Reliability, vol. 18, no. 2, pp. 205–213, 2018. View at Publisher · View at Google Scholar