A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

Table 1

Simulation parameters.

Parameter	Value
𝑊min	360 nm
𝐿min	140 nm
𝐶min	1.24 fF
𝑉DD	1.8 V
Frequency	250 MHz
Signal slope	100 ps