A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

Table 2

Traditional transmission gate flip-flop at 19.92 fF load (16X).

𝐶in (fF)	𝑤1	𝑤2	𝑤3	𝑤4	𝑇DQ,min (ps)	Power (uW)	PDP (fJ)
2.48	2	2.35	2.79	6.65	226	554	125.2
4.96	4	3.95	3.95	7.91	191	585	111.7
7.44	6	5.35	4.84	8.76	173	599	103.6
9.92	8	6.65	5.59	9.41	166	615	102
12.4	10	7.86	6.25	9.95	162	632	102.3
14.8	12	9.01	6.85	10.4	159	648	103
17.3	14	10.1	7.40	10.8	157	665	104.4
19.8	16	11.1	7.91	11.2	155	675	104.6
22.3	18	12.2	8.39	11.5	154	682	105
24.8	20	13.2	8.84	11.8	153	689	105.4