A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

Table 3

Technology parameters used for estimation of capacitances.

Parameter	𝐶gdo (F/m)	𝐶gso (F/m)	𝐶jsw (F/m)	𝐶𝑗 (F/m^2)	𝐿𝐷 (m)	𝐿𝑆 (m)
NMOS	2.78𝐸−10	2.78𝐸−10	7.9𝐸−10	0.00365	31.6𝐸−09	31.6𝐸−09
PMOS	2.78𝐸−10	2.78𝐸−10	1.44𝐸−9	0.00138	31.6𝐸−09	31.6𝐸−09