A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

Table 4

Comparison of flip-flop parameters at 𝐶_in=12.4 fF and 16X capacitive loading.

Design	TGFF	mC^2MOSff1	WPMS	PTLFF	GMSL	DTLA
Transistor count	20	16	24	16	31	46
No. of clocked transistors	8	6	6	4	2	3
Clock-to-output delay (ps)	92	116	206	204	419	683
Optimum setup time (ps)	70	80	40	50	80	−140
Hold time (ps)	−19	−21	−33	−32	−23	25
𝑇DQ,min (ps)	162	196	246	254	499	543
Clock load (fF)	16.44	23.02	9.05	8.22	7.76	7.31
Power dissipation (uW)*	632	640	786	679	676	643
Leakage Power (uW)	59.38	57.51	72.64	69.83	74.91	76.73

∗Pseudorandom sequence with 𝛼=0.5 is used for power calculations.