Table 4: Comparison of flip-flop parameters at  fF and 16X capacitive loading.

DesignTGFFmC2MOSff1WPMSPTLFFGMSLDTLA

Transistor count201624163146
No. of clocked transistors866423
Clock-to-output delay (ps)92116206204419683
Optimum setup time (ps)7080405080−140
Hold time (ps)−19−21−33−32−2325
(ps)162196246254499543
Clock load (fF)16.4423.029.058.227.767.31
Power dissipation (uW)*632640786679676643
Leakage Power (uW)59.3857.5172.6469.8374.9176.73

Pseudorandom sequence with is used for power calculations.