A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

Table 6

Flip-flop simulation parameters at 65 nm CMOS technology.

Process corner	Temperature (°C)	𝑉DD	Simulation/technology parameters
TT	70	1	𝐿min	𝑊min	𝐶min	Frequency	Signal slope
FF	0	1.1	60 nm	120 nm	507 aF	2 GHz	20 ps
SS	125	0.9
FS	70	1	𝐶Poly=0.268 𝐶𝐺		𝐶metal1=0.215 𝐶𝐺		𝐶metal2=0.175 𝐶𝐺
SF	70	1