Effects of Gate Stack Structural and Process Defectivity on High- Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs
Figure 7
Threshold voltage shift for different SiO2 IL thickness during the (a) stress phase and (b) relaxation phase as a function of stress and relaxation time, respectively. Time evolution of hole trap density, , and interface trap density, , for different SiO2 IL thickness during the (c) stress phase and the (d) relaxation phase as a function of stress and relaxation time, respectively.
