Research Article
Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture
Table 5
Description of the platforms used for the experiments with power analysis.
| | Xilinx FPGAs | Altera FPGAs |
| Family | Virtex-II | Virtex-II | Spartan-3 | Cyclone II | Device | XC2VP30 | XC2VP50 | XC2S200 | EP2C35 | Speed grade | −5 | −5 | −5 | 6 | Design voltage (V) | 1.4 | 1.4 | 1.2 | 1.2 | Max. clock frequency (MHz) | 205 | 205 | 163.84 | 191.79 | Static power (mW) | 768 | 768 | 44 | 83 | Dynamic power (mW) | 66 | 66 | 23 | 42 |
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