Research Article
Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor
Table 1
The summarized comparison with other types of column-parallel architectures.
| Specification | This work | Two-step SSADC [5] | Cyclic ADC [4] | Calibrated SAR ADC [3] |
| Process | 0.18 µm | 0.25 µm | 0.25 µm | 0.18 µm | Quantization resolution | 11-bit | 10-bit | 12-bit | 10-bit | Chip area | 7 × 500 µm2 | 7.4 µm pitch | 40 × 2200 µm2 | 14 × 700 µm2 | Power consumption | 5 µW at 40 Ksamples/s | 75 µW at 60 Ksamples/s | 1.9 mW (full chip) at 1.9 Msamples/s | 1.5 mW (full chip) at 2 Msamples/s | Quantization cycles | 24 cycles/sample | >160 cycles/sample | 12 cycles/sample | 13 cycles/sample | DNL | +0.5/−1 LSB | <+/−1 LSB | +0.76/−0.81 LSB | 0.34 LSB | FOM1 Energy efficiency | 125 pJ/sample ADC core | 1250 pJ/sample ADC core | 1 nJ/sample full chip | 750 pJ/sample full chip | FOM2 Area efficiency | 84 k µm2·cycles/sample | — | 1056 k µm2·cycles/sample | 127 k µm2·cycles/sample |
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