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The Scientific World Journal
Volume 2014 (2014), Article ID 982569, 9 pages
http://dx.doi.org/10.1155/2014/982569
Research Article

Modeling and Simulation of Network-on-Chip Systems with DEVS and DEUS

Centro Interdipartimentale SITEIA.PARMA, Università degli Studi di Parma, Parco Area delle Scienze 181a, 43124 Parma, Italy

Received 30 August 2013; Accepted 13 February 2014; Published 17 April 2014

Academic Editors: J. Sarangapani and A. Zaravinos

Copyright © 2014 Michele Amoretti. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Networks on-chip (NoCs) provide enhanced performance, scalability, modularity, and design productivity as compared with previous communication architectures for VLSI systems on-chip (SoCs), such as buses and dedicated signal wires. Since the NoC design space is very large and high dimensional, evaluation methodologies rely heavily on analytical modeling and simulation. Unfortunately, there is no standard modeling framework. In this paper we illustrate how to design and evaluate NoCs by integrating the Discrete Event System Specification (DEVS) modeling framework and the simulation environment called DEUS. The advantage of such an approach is that both DEVS and DEUS support modularity—the former being a sound and complete modeling framework and the latter being an open, general-purpose platform, characterized by a steep learning curve and the possibility to simulate any system at any level of detail.