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The Scientific World Journal
Volume 2015, Article ID 327357, 8 pages
http://dx.doi.org/10.1155/2015/327357
Research Article

A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications

1Department of Electronics and Communication Engineering, PSNA College of Engineering and Technology, Dindigul 624622, India
2Department of Computer Science and Engineering, RVS Educational Trust Group of Institutions, Dindigul 624005, India

Received 19 October 2014; Revised 17 March 2015; Accepted 19 March 2015

Academic Editor: Yo-Sheng Lin

Copyright © 2015 M. Revathy and R. Saravanan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.