Low Power Systolic Array Based Digital Filter for DSP Applications

Table 2

Results of multiplier with existing and proposed compressor architecture.

Design	Multiplier
	With existing compressor of [7]	With existing compressor of [6]	Existing (TSMC library compressor cell)	Proposed
Area	859.68	711.36	668.759	801
Delay	2.48	1.72	1.47	2.72
DP	177.8	173.3	162.8	171.9
LP	8.45	9.28	8.45	6.88
TP	186.25	182.58	171.25	178.78

Note: “area” in square microns; “delay” in nanoseconds; “DP” dynamic power in microwatt; “LP” leakage power in microwatt; “TP” total power in microwatt.