Low Power Systolic Array Based Digital Filter for DSP Applications

Table 3

Results of digital filter with existing and proposed compressor architecture.

Design	Digital filter
	With existing compressor of [7]	With existing compressor of [6]	Existing (TSMC library compressor cell)	Proposed
Area	9793.8	9200.52	9027.72	9559
Delay	3.45	3.45	3.45	3.63
DP	434.7	432.8	429.2	432.9
LP	104	107	104	97.9
TP	538.7	539.8	533.2	530.8

Note: “area” in square microns; “delay” in nanoseconds; “DP” dynamic power in microwatt; “LP” leakage power in microwatt; “TP” total power in microwatt.