An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Table 1

Comparison of parameters of synchronous Viterbi decoder for various constraint lengths.

Parameters
Constraint length ()	Transistor count	Power consumption	Frequency	Delay
4	1520	106.46 mW	330 MHz	3.22 ms
5	2067	114.16	398 MHz	2.51 ms
6	2648	158.09	469 MHz	2.13 ms
7	3152	188.26	512 MHz	1.95 ms