NULL Convention Floating Point Multiplier

Table 6

Comparison of existing and proposed NCL multipliers.

NCL circuits	Multiplication scheme			CMOS technology	(ns)	Power	Area
	Nonfractional	Fixed point	Floating point
4-bit × 4-bit unsigned multiplier [9]	✓	—	—	3.3 V, 0.5 μm	9.21	3.34 nW	2004 transistors
4-bit × 4-bit unsigned booth multiplier [10]	✓	—	—	1.8 V, 0.18 μm	5.87	—	—
72 + 32 × 32 bit multiply and accumulate unit [3]	—	✓	—	3.3 V, 0.5 μm	11.4	—	16,169 gates
2’s complement 8 × 8 bit pipelined multiplier [11]	✓	—	—	1.8 V, 0.18 μm	5.638	—	330836 μm^2
32-bit FFT utilizing 16 × 16 bit array multiplier [5]	—	✓	—	1.8 V, 0.18 μm	452	—	4983104 transistors
Nonpipelined FIR filter utilizing 8 × 8 bit unsigned multiplier [12]	✓	—	—	IBM 130 nm	13.35	—	6831 gates
Proposed NCL floating point multiplier, compliant with 32-bit single precision IEEE 754 standard	—	—	✓	1.8 V, 0.18 μm	5.672	3.163 mW	175281 μm^2