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The Scientific World Journal
Volume 2015 (2015), Article ID 752969, 14 pages
Research Article

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

1Department of Electronics and Computer Technology, University of Granada, Campus Universitario Fuentenueva, 18071 Granada, Spain
2Instituto de Investigación en Tecnología Informática Avanzada (INTIA), Universidad Nacional del Centro de la Provincia de Buenos Aires (UNCPBA), B7001BBO Tandil, Argentina
3Department of Electrical and Computer Engineering, Florida State University (FSU), 2525 Pottsdamer Street, Tallahassee, FL 32310, USA

Received 4 September 2014; Accepted 17 February 2015

Academic Editor: Andrzej Materka

Copyright © 2015 E. Castillo et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


HDL-level design offers important advantages for the application of watermarking to IP cores, but its complexity also requires tools automating these watermarking algorithms. A new tool for signature distribution through combinational logic is proposed in this work. IPP@HDL, a previously proposed high-level watermarking technique, has been employed for evaluating the tool. IPP@HDL relies on spreading the bits of a digital signature at the HDL design level using combinational logic included within the original system. The development of this new tool for the signature distribution has not only extended and eased the applicability of this IPP technique, but it has also improved the signature hosting process itself. Three algorithms were studied in order to develop this automated tool. The selection of a cost function determines the best hosting solutions in terms of area and performance penalties on the IP core to protect. An 1D-DWT core and MD5 and SHA1 digital signatures were used in order to illustrate the benefits of the new tool and its optimization related to the extraction logic resources. Among the proposed algorithms, the alternative based on simulated annealing reduces the additional resources while maintaining an acceptable computation time and also saving designer effort and time.