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The Scientific World Journal
Volume 2015, Article ID 752969, 14 pages
http://dx.doi.org/10.1155/2015/752969
Research Article

Design Time Optimization for Hardware Watermarking Protection of HDL Designs

1Department of Electronics and Computer Technology, University of Granada, Campus Universitario Fuentenueva, 18071 Granada, Spain
2Instituto de Investigación en Tecnología Informática Avanzada (INTIA), Universidad Nacional del Centro de la Provincia de Buenos Aires (UNCPBA), B7001BBO Tandil, Argentina
3Department of Electrical and Computer Engineering, Florida State University (FSU), 2525 Pottsdamer Street, Tallahassee, FL 32310, USA

Received 4 September 2014; Accepted 17 February 2015

Academic Editor: Andrzej Materka

Copyright © 2015 E. Castillo et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

E. Castillo, D. P. Morales, A. García, L. Parrilla, E. Todorovich, and U. Meyer-Baese, “Design Time Optimization for Hardware Watermarking Protection of HDL Designs,” The Scientific World Journal, vol. 2015, Article ID 752969, 14 pages, 2015. https://doi.org/10.1155/2015/752969.