Design Time Optimization for Hardware Watermarking Protection of HDL Designs

Table 1

HDAs and CTs (PentiumIV at 2.2 GHz) with the automated tool for the sum as combinational logic (^*resources exceeded).

DS	SBL	RLA		EPO		SAMB
		HDA	CT (s)	HDA	CT (s)	HDA	CT (s)
MD5	2	78	0.032	43	0.084	44	8.04
	4	99	0.046	53	0.120	55	7.25
	6	109	0.051	55	0.410	56	5.16
	8	106	0.053	50	4.280	51	4.74
	10	110	0.050	49	166.8	52	4.56
	12	110	0.016	*	*	52	5.08
	16	105	0.021	*	*	53	4.20
	20	96	0.020	*	*	50	4.77
	24	80	0.020	*	*	41	5.30
	30	64	0.023	*	*	32	5.70
SHA1	2	99	0.130	55	0.150	55	9.11
	4	125	0.170	68	0.150	70	7.71
	6	136	0.078	67	1.410	69	8.89
	8	135	0.037	62	23.90	63	6.77
	10	139	0.036	63	195.9	64	6.31
	12	146	0.025	*	*	67	7.15
	16	136	0.023	*	*	69	5.40
	20	112	0.041	*	*	57	5.43
	24	96	0.030	*	*	49	6.83
	30	81	0.022	*	*	40	6.90