Design Time Optimization for Hardware Watermarking Protection of HDL Designs

Table 2

HDAs and CTs (PentiumIV at 2.2 GHz) with the automated tool for the linear combination as combinational logic (^*resources exceeded).

DS	SBL	RLA		EPO		SAMB
		HDA	CT (s)	HDA	CT (s)	HDA	CT (s)
MD5	2	99	0.06	24	0.7	25	5.2
	4	110	0.02	32	0.6	34	3.8
	6	123	0.01	54	0.2	59	4.7
	8	119	0.01	47	2.6	50	6.6
	10	117	0.01	40	54	46	7.0
	12	118	0.03	*	*	46	12
	16	112	0.15	*	*	51	35
	20	113	0.13	*	*	59	156
	24	120	1.16	*	*	65	383
	30	120	11.0	*	*	70	2000
SHA1	2	122	0.09	30	0.3	32	6.7
	4	136	0.02	41	0.4	42	4.9
	6	152	0.01	66	0.2	72	6.0
	8	149	0.03	65	5.3	64	7.4
	10	148	0.02	50	152	57	9.2
	12	155	0.05	*	*	61	18
	16	142	0.26	*	*	64	44
	20	139	0.95	*	*	68	103
	24	143	1.09	*	*	77	730
	30	150	9.08	*	*	88	4200