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The Scientific World Journal
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2015
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Article
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Fig 9
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Research Article
A New Arbiter PUF for Enhancing Unpredictability on FPGA
Figure 9
Design of the 3-1 Double Arbiter PUF on Xilinx Virtex-5 FPGA. SR-Latches as Arbiters are fabricated by pairing the NAND with LookUp Table (LUT).