The Scientific World Journal / 2015 / Article / Fig 9

Research Article

A New Arbiter PUF for Enhancing Unpredictability on FPGA

Figure 9

Design of the 3-1 Double Arbiter PUF on Xilinx Virtex-5 FPGA. SR-Latches as Arbiters are fabricated by pairing the NAND with LookUp Table (LUT).