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VLSI Design
Volume 1, Issue 2, Pages 99-111
http://dx.doi.org/10.1155/1994/46871

Building Rectangular Floorplans–A Graph Theoretical Approach

Systems Engineering and Design Automation Laboratory, Sydney University Electrical Engineering, New South Wales 2006, Australia

Received 22 November 1988; Revised 25 March 1990

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Rectangular dualisation is a technique used to generate rectangular topologies for use in top-down floorplanning of integrated circuits. In order for this technique to be used in a floorplanning system, its input, the connectivity graph representing an integrated circuit has to fulfill a number of conditions. This paper presents an efficient algorithm that transforms an arbitrary connected graph, representing an integrated circuit, into another graph that is guaranteed to fulfill these conditions and to admit rectangular duals. Effectively, the algorithm solves the global routing problem by using three techniques: passthrough, wiring blocks and collapsed wiring blocks. Resulting floorplans may be passed to a chip assembler and detailed router package to complete the layout. This paper also introduces a novel technique to transform a tree of biconnected sub-graphs into a block neighbourhood graph that is a path.