VLSI Design

Table of Contents: 1994

  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 039791

Integrated Test Solutions for a System Design Environment

Kevin T. Kornegay | Robert W. Brodersen
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 082606

An Approach for Self-Checking Realization of Interacting Finite State Machines

Fadi Busaba | Parag K. Lala
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 036218

STD Architecture: A Practical Approach to Test M-Bits Random Access Memories

Rochit Rajsuman | Kamal Rajkanan
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 078932

Empirical Bounds on Fault Coverage Loss Due to LFSR Aliasing

Warren H. Debany | Mark J. Gorniak | ... | Heather B. Dussault
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 031646

Partial Reset: An Alternative DFT Approach

Ben Mathew | Daniel G. Saab
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 074269

Optimal Testing and Design of Adders

Michael J. Batek | John P. Hayes
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 027973

Resolution Enhancement in IDDQ Testing for Large ICs

Yashwant K. Malaiya | Anura P. Jayasumana | ... | Sankaran M. Menon
  • VLSI Design -
  • Special Issue
  • - Volume 2
  • - Article ID 083851

Modular Scheme for Designing Special Purpose Associative Memories and Beyond

A. R. Hurson | S. Pakzad
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 070696

Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits

M. O. Esonu | D. Al-Khalili | C. Rozon
  • VLSI Design -
  • Special Issue
  • - Volume 2
  • - Article ID 037474

An Improved Data Flow Architecture for Logic Simulation Acceleration

A. Mahmood | J. Herath | J. Jayasumana
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 024312

Special Issue on Digital Hardware Testing

Rochit Rajsuman
  • VLSI Design -
  • Special Issue
  • Volume 1
  • - Article ID 067035

Block-Level Logic Extraction from CMOS VLSI Layouts

Inderpreet Bhasin | Joseph G. Tront
  • VLSI Design -
  • Special Issue
  • - Volume 2
  • - Article ID 080287

SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm

Chi-Yu Mao | Yu Hen Hu
  • VLSI Design -
  • Special Issue
  • Volume 1
  • - Article ID 019638

An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model

Xiaoyu Song
  • VLSI Design -
  • Special Issue
  • - Volume 2
  • - Article ID 032902

TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing

C. P. Ravikumar | H. Rasheed

We are committed to sharing findings related to COVID-19 as quickly and safely as possible. Any author submitting a COVID-19 paper should notify us at help@hindawi.com to ensure their research is fast-tracked and made available on a preprint server as soon as possible. We will be providing unlimited waivers of publication charges for accepted articles related to COVID-19. Sign up here as a reviewer to help fast-track new submissions.