VLSI Design

Table of Contents: 1994

  • VLSI Design -
  • Special Issue
  • - Volume 2
  • - Article ID 013748

Pioneer: A New Tool for Coding of Multi-Level Finite State Machines Based on Evolution Programming

S. Muddappa | R. Z. Makki | ... | S. Isukapalli
  • VLSI Design -
  • Special Issue
  • - Volume 2
  • - Article ID 056371

Technology Mapping for FPGA Using Generalized Functional Decomposition

Kuo-Hua Wang | Cheng Chen | Ting Ting Hwang
  • VLSI Design -
  • Special Issue
  • - Volume 2
  • - Article ID 098085

Preface

Si-Qing Zheng | Dian Zhou
  • VLSI Design -
  • Special Issue
  • Volume 2
  • - Article ID 051798

Analysis and Characterization of State Assignment Techniques for Sequential Machines

R. Z. Makki | S. Su
  • VLSI Design -
  • Special Issue
  • Volume 2
  • - Article ID 094514

Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits

Anand V. Hudli | Raghu V. Hudli
  • VLSI Design -
  • Special Issue
  • Volume 2
  • - Article ID 048137

On Channel Routing Problems With Interchangeable Terminals

Spyros Tragoudas
  • VLSI Design -
  • Special Issue
  • Volume 2
  • - Article ID 090841

High Throughput Error Control Using Parallel CRC

Andrzej Sobski | Alexander Albicki
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 039791

Integrated Test Solutions for a System Design Environment

Kevin T. Kornegay | Robert W. Brodersen
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 082606

An Approach for Self-Checking Realization of Interacting Finite State Machines

Fadi Busaba | Parag K. Lala
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 036218

STD Architecture: A Practical Approach to Test M-Bits Random Access Memories

Rochit Rajsuman | Kamal Rajkanan
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 078932

Empirical Bounds on Fault Coverage Loss Due to LFSR Aliasing

Warren H. Debany | Mark J. Gorniak | ... | Heather B. Dussault
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 031646

Partial Reset: An Alternative DFT Approach

Ben Mathew | Daniel G. Saab
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 074269

Optimal Testing and Design of Adders

Michael J. Batek | John P. Hayes
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 027973

Resolution Enhancement in IDDQ Testing for Large ICs

Yashwant K. Malaiya | Anura P. Jayasumana | ... | Sankaran M. Menon
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 070696

Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits

M. O. Esonu | D. Al-Khalili | C. Rozon

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