VLSI Design

VLSI Design / 1994 / Article

Open Access

Volume 1 |Article ID 067035 | https://doi.org/10.1155/1994/67035

Inderpreet Bhasin, Joseph G. Tront, "Block-Level Logic Extraction from CMOS VLSI Layouts", VLSI Design, vol. 1, Article ID 067035, 17 pages, 1994. https://doi.org/10.1155/1994/67035

Block-Level Logic Extraction from CMOS VLSI Layouts

Received30 Aug 1990
Revised21 Feb 1991

Abstract

This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level description of a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to that of a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors, resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be used to identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to the circuit hierarchy. Basic gates such as inverters, transmission-gates, nands, nors, etc. are identified first. Logic blocks composed of these gates are then identified. More complex blocks which contain blocks already identified are recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It can provide a connectivity check for a circuit.

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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