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VLSI Design
Volume 1, Issue 3, Pages 243-259
http://dx.doi.org/10.1155/1994/67035

Block-Level Logic Extraction from CMOS VLSI Layouts

Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA

Received 30 August 1990; Revised 21 February 1991

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level description of a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to that of a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors, resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be used to identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to the circuit hierarchy. Basic gates such as inverters, transmission-gates, nands, nors, etc. are identified first. Logic blocks composed of these gates are then identified. More complex blocks which contain blocks already identified are recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It can provide a connectivity check for a circuit.