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VLSI Design
Volume 3 (1995), Issue 3-4, Pages 301-313

Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions

1Department of Electrical Engineering, Portland State University, Portland 97207, OR, USA
2Arkos Design Inc., 5619 Scotts Valley Drive, Scotts Valley 95066, CA , USA

Copyright © 1995 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introduced families include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams can provide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams (KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and are created here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction of KDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families of functional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean Kronecker Ternary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuit realization. There are two variants of each of the last two families: canonical and non-canonical. While the canonical diagrams can be used as efficient general-purpose Boolean function representations, the non-canonical variants are also applicable to incompletely specified functions and create don't cares in the process of the creation of the diagram.. They lead to even more compact circuits in logic synthesis and technology mapping.