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VLSI Design
Volume 4, Issue 2, Pages 107-118
http://dx.doi.org/10.1155/1996/13931

An Integrated Hardware Array for Very High Speed Logic Simulation

1Applied Research Laboratories, The University of Texas at Austin, USA
2Electrical and Computer Engineering, The University of Texas at Austin, USA

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

E. Scott Fehr, Stephen A. Szygenda, and Granville E. Ott, “An Integrated Hardware Array for Very High Speed Logic Simulation,” VLSI Design, vol. 4, no. 2, pp. 107-118, 1996. https://doi.org/10.1155/1996/13931.