VLSI Design

Table of Contents: 1996

  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 053238

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

Srilata Raman | C. L. Liu | Larry G. Jones
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 095942

DP-FPGA: An FPGA Architecture Optimized for Datapaths

Don Cherepacha | David Lewis
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 049565

A Timing-Driven Partitioning System for Multiple FPGAs

Kalapi Roy | Carl Sechen
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 092380

A Sea-of-Gates Style FPGA Placement Algorithm

Kalapi Roy | Bingzhong (David) Guan | Carl Sechen
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 045983

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

Stephen Brown | Muhammad Khellah | Guy Lemieux
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 087608
  • - Editorial

Field-Programmable Gate Arrays

Dinesh Bhatia
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 041420

Erratum

  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 084045

A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays

S. Bandyopadhyay | A. Sengupta | B. B. Bhattacharya
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 037648

A Modified Approach to Test Plan Generation for Combinational Logic Blocks

Anupam Basu | Dilip K. Banerji | ... | Jay C. Majithia
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 080472

Fault Modeling of ECL for High Fault Coverage of Physical Defects

Sankaran M. Menon | Yashwant K. Malaiya | Anura P. Jayasumana
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 034084

Switch-level Differential Fault Simulation of MOS VLSI Circuits

Evstratios Vandris | Gerald Sobelman
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 075798

On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach

M. Srinivas | L. M. Patnaik
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 029412

Closed Form Aliasing Probability For Q-ary Symmetric Errors

Geetani Edirisooriya
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 072136

HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits

Kyuchull Kim | Kewal K. Saluja
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 025839

A Novel Path Delay Fault Simulator Using Binary Logic

Ananta K. Majhi | James Jacob | Lalit M. Patnaik

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