VLSI Design

Table of Contents: 1996

  • VLSI Design -
  • Special Issue
  • Volume 4
  • - Article ID 094696

Design and Implementation of a Low Power Ternary Full Adder

A. Srivastava | K. Venkatapathy
  • VLSI Design -
  • Special Issue
  • Volume 5
  • - Article ID 069892

High-Level Graphical Abstraction in Digital Design

Murray W. Pearson | Paul J. Lyons | Mark D. Apperley
  • VLSI Design -
  • Special Issue
  • Volume 5
  • - Article ID 023706

Zener Zap Anti-Fuse Trim in VLSI Circuits

Donald T. Comer
  • VLSI Design -
  • Special Issue
  • Volume 4
  • - Article ID 048310

Integration of SPICE with TEK LV500 ASIC Design Verification System

A. Srivastava | S. R. Palavali
  • VLSI Design -
  • Special Issue
  • Volume 5
  • - Article ID 065320

TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis

C. P. Ravikumar | V. Saxena
  • VLSI Design -
  • Special Issue
  • Volume 4
  • - Article ID 091035

Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures

Ausif Mahmood
  • VLSI Design -
  • Special Issue
  • Volume 5
  • - Article ID 019043

A New Theory for Testability-Preserving Optimization of Combinational Circuits

Jiabi Zhu | Mostafa Abd-El-Barr | Carl McCrosky
  • VLSI Design -
  • Special Issue
  • Volume 4
  • - Article ID 043738

Minimum-Cost Node-Disjoint Steiner Trees in Series-Parallel Networks

Sunil Chopra | Kalyan T. Talluri
  • VLSI Design -
  • Special Issue
  • Volume 4
  • - Article ID 086362

An Efficient Algorithm for the Split K-Layer Circular Topological Via Minimization Problem

J. S. Huang | Y. H. Chin
  • VLSI Design -
  • Special Issue
  • Volume 5
  • - Article ID 061747

Improving Path Sensitizability of Combinational Circuits

Bhanu Kapoor | V. S. S. Nair
  • VLSI Design -
  • Special Issue
  • Volume 5
  • - Article ID 058084

A Fast Clustering-Based Min-Cut Placement Algorithm With Simulated-Annealing Performance

Youssef Saab
  • VLSI Design -
  • Special Issue
  • Volume 4
  • - Article ID 040175

Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs

D. Bhagavathi | H. Gurla | ... | J. Zhang
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 053238

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

Srilata Raman | C. L. Liu | Larry G. Jones
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 095942

DP-FPGA: An FPGA Architecture Optimized for Datapaths

Don Cherepacha | David Lewis
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 049565

A Timing-Driven Partitioning System for Multiple FPGAs

Kalapi Roy | Carl Sechen

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