Table of Contents
VLSI Design
Volume 4, Issue 2, Pages 135-139

The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

1Department of Electronics, University of York, York YO1 5DD, UK
2Department of Electrical Engineering and Electronics, UMIST, Manchester M60 1QD, UK

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [1 citation]

The following is the list of published articles that have cited the current article.

  • Bouthaina Dammak, Mouna Baklouti, Rachid Benmansour, Smail Niar, and Mohamed Abid, “Hardware resource utilization optimization in FPGA-based Heterogeneous MPSoC architectures,” Microprocessors and Microsystems, 2015. View at Publisher · View at Google Scholar