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VLSI Design
Volume 4 (1996), Issue 1, Pages 33-40
http://dx.doi.org/10.1155/1996/40175

Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs

1Department of Computer Science, Old Dominion University, Norfolk 23529-0162, VA, USA
2Department of Math and Computer Science, Elizabeth City State University, Elizabeth City 27909, NC, USA
3Department of Computer Science, Old Dominion University, Norfolk 23529-0162, VA, USA

Received 17 December 1992; Revised 30 July 1993

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The compaction step of integrated circuit design motivates associating several kinds of graphs with a collection of non-overlapping rectangles in the plane. These graphs are intended to capture various visibility relations amongst the rectangles in the collection. The contribution of this paper is to propose time- and cost-optimal algorithms to construct two such graphs, namely, the dominance graph (DG, for short) and the visibility graph (VG, for short). Specifically, we show that with a collection of n non-overlapping rectangles as input, both these structures can be constructed in θ(log n) time using n processors in the CREW model.