VLSI Design

VLSI Design / 1996 / Article

Open Access

Volume 5 |Article ID 053512 | https://doi.org/10.1155/1996/53512

Dinesh Bhatia, V. Shankar, "Greedy Segmented Channel Router", VLSI Design, vol. 5, Article ID 053512, 11 pages, 1996. https://doi.org/10.1155/1996/53512

Greedy Segmented Channel Router

Received03 Aug 1994
Accepted03 Feb 1996

Abstract

An efficient solution to the generalized detailed routing problem in segmented channels for row-based FPGAs is presented. A generalized detailed routing allows routing of each connection using an arbitrary number of tracks, i.e., doglegs are allowed. This approach is different from the normally followed method where each connection is routed on a single straight track. We present a router that performs generalized segmented channel routing using a greedy approach to route channels. The router also renders itself to limited tolerance against faults in the routing architecture.

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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