Table of Contents
VLSI Design
Volume 5, Issue 1, Pages 11-21

Greedy Segmented Channel Router

1Design Automation Laboratory, Department of Electrical and Computer Engineering & Computer Science, P.O. Box 210030, University of Cincinnati, Cincinnati, OH 45221-0030, USA
2Mail Stop: JF1-61, 2111 N.E. 25th Ave., Intel Corporation, 97124-5961, Hillsboro, OR, USA

Received 3 August 1994; Accepted 3 February 1996

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


An efficient solution to the generalized detailed routing problem in segmented channels for row-based FPGAs is presented. A generalized detailed routing allows routing of each connection using an arbitrary number of tracks, i.e., doglegs are allowed. This approach is different from the normally followed method where each connection is routed on a single straight track. We present a router that performs generalized segmented channel routing using a greedy approach to route channels. The router also renders itself to limited tolerance against faults in the routing architecture.