VLSI Design

VLSI Design / 1996 / Article

Open Access

Volume 4 |Article ID 079127 | https://doi.org/10.1155/1996/79127

Dinesh Bhatia, Amit Chowdhary, "A Multi-Terminal Net Router for Field-Programmable Gate Arrays", VLSI Design, vol. 4, Article ID 079127, 10 pages, 1996. https://doi.org/10.1155/1996/79127

A Multi-Terminal Net Router for Field-Programmable Gate Arrays

Received22 Dec 1993
Revised18 Oct 1994


This paper presents a router for routing multi-terminal nets in field-programmable gate arrays (FPGAs). The router does not require pre-assignment of routing channels, a phase that is normally accomplished during global routing. This direct routing approach greatly enhances the probability of routing (routability). The multi-terminal routing greatly reduces the total wire length as it approximates a Steiner tree. The total number of segments required to route the circuits is usually less as compared to other routing approaches. The router has generated excellent routing results for some industrial circuits. The memory requirements for this router are very low. The time needed for the routing is linear with respect to the size of the circuit.

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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