Table of Contents
VLSI Design
Volume 4, Issue 1, Pages 1-10

A Multi-Terminal Net Router for Field-Programmable Gate Arrays

1Design Automation Laboratory, Department of Electrical & Computer Engineering and Computer Science, P.O. Box 210030, University of Cincinnati, Cincinnati 45221-0030, OH, USA
2Amit Chowdhary Department of Electrical Engineering and Computer Science, University of Michigan, 1301 Beal Avenue, Ann Arbor 48109-2122, MI, USA

Received 22 December 1993; Revised 18 October 1994

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [4 citations]

The following is the list of published articles that have cited the current article.

  • J.M. Emmert, and D. Bhatia, “Incremental routing in FPGAs,” Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372), pp. 217–221, . View at Publisher · View at Google Scholar
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