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VLSI Design
Volume 5, Issue 2, Pages 125-140
http://dx.doi.org/10.1155/1997/30941

Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits

1View Logic Systems, 47211 Lake View Blvd. Fremont, 94538, CA, USA
2Consultant, 7 Skylonda Drive, Woodside, 94062, CA, USA
3Mentor Graphics, 1001 Ridder Park Drive, San Jose 95131, CA, USA

Copyright © 1997 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Mandalagiri S. Chandrasekhar, Robert H. McCharles, and David E. Wallace, “Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits,” VLSI Design, vol. 5, no. 2, pp. 125-140, 1997. https://doi.org/10.1155/1997/30941.