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VLSI Design
Volume 5 (1997), Issue 2, Pages 141-153

Statistical Module Level Area and Delay Estimation

Department of Computer Science, Iowa State University, Ames, Iowa 50011-1040, USA

Copyright © 1997 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The increasing complexity of VLSI design process has led to an increasing use of layout synthesis systems. For many components of a high-level synthesis system such as module generators and module generator development environments, an accurate model of area and delay for the layouts generated by a layout synthesis system is extremely desirable. We have experimented with a statistical model for area and delay of function modules. This model is surprisingly accurate for a standard cell based layout synthesis systemૼVPNR. The area of adder and shifter modules can be modeled to with in 5% accuracy while the error in delay model is bounded by 4%. This model can be taken through another level of indirection without significant loss in accuracy. The area of all the modules that fit a ripple-template (such as carry-ripple adder) can be modeled with in 30% accuracy. The delay of these modules has a better fit, 15%. The square-template designs (such as array multiplier) have an area model with 1.7% coeificient of variance. In these cases, the model is parametrized by the area and delay of the leaf cells in the template.