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VLSI Design
Volume 5, Issue 2, Pages 141-153
http://dx.doi.org/10.1155/1997/78238

Statistical Module Level Area and Delay Estimation

Department of Computer Science, Iowa State University, Ames, Iowa 50011-1040, USA

Copyright © 1997 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Akhilesh Tyagi, “Statistical Module Level Area and Delay Estimation,” VLSI Design, vol. 5, no. 2, pp. 141-153, 1997. https://doi.org/10.1155/1997/78238.