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VLSI Design
Volume 5 (1997), Issue 2, Pages 195-209

Datapath Optimization Using Layout Information: An Empirical Study

Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30043, China

Received 1 January 1993; Accepted 1 December 1993

Copyright © 1997 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Most datapath synthesis approaches use a simple area model to evaluate design area quality. However, using such a simplified model could mislead synthesis tasks into generating inferior designs. This paper presents an extensive experimental study to validate the correlation between the tradition area model, our proposed area model, and the actual layouts. The results show that traditional area quality measures are not good indicators for optimization in datapath synthesis. Moreover, this paper also shows that to provide accurate indications for design tradeoffs in high-level synthesis, the fidelity of the estimates is more important than the accuracy.