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VLSI Design
Volume 7 (1998), Issue 1, Pages 97-110

Placement and Routing for Performance-Oriented FPGA Layout

1School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA 99164-2752, USA
2Department of Computer Science, University of Virginia, Charlottesville, VA 22903-2442, USA
3Cadence Design Systems, lnc., San Jose, CA 95134-1937, USA

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route several benchmarks.