Jun-Dong  Cho

Guest Editorial

The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication
technology rapidly evolves. Accordingly, it becomes important to minimize crosstalk
caused by the coupling capacitance between adjacent wires in the layout design for the
fast and safe VLSI circuits. We present a simulated annealing approach based on
segment rearrangement to crosstalk minimization in an initially gridded channel
routing. The proposed technique is compared with previous track-oriented techniques,
especially a track permutation technique whose performance is bounded by an
exhaustive track permutation algorithm. Experiments showed that the presented
technique is more effective than the track permutation technique.

Kyoung-Son Jhang

Soonhoi Ha

Chu Shik Jhon

Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing

Given a set of terminals on the plane <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>N</mml:mi><mml:mo>=</mml:mo><mml:mrow><mml:mo>{</mml:mo><mml:mrow><mml:mi>s</mml:mi><mml:mo>,</mml:mo><mml:msub><mml:mi>ν</mml:mi><mml:mn>1</mml:mn></mml:msub><mml:mo>,</mml:mo><mml:mo>…</mml:mo><mml:mo>,</mml:mo><mml:msub><mml:mi>ν</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow><mml:mo>}</mml:mo></mml:mrow></mml:math>, with a source terminal s, a
Rectilinear Distance-Preserving Tree (RDPT) T(V, E) is defined as a tree rooted at s,
connecting all terminals in N. An RDPT has the property that the length of every source
to sink path is equal to the rectilinear distance between that source and sink. A Min-
Cost Rectilinear Distance-Preserving Tree (MRDPT) minimizes the total wire length
while maintaining minimal source to sink linear delay, making it suitable for high
performance interconnect applications.This paper studies problems in the construction of RDPTs, including the following
contributions. A new exact algorithm for a restricted version of the problem in one
quadrant with O<mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mn>2</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> time complexity is proposed. A novel heuristic algorithm, which
uses optimally solvable sub-problems, is proposed for the problem in a single quadrant.
The average and worst-case time complexity for the proposed heuristic algorithm are O<mml:math id="E3" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mrow><mml:mrow><mml:mn>3</mml:mn><mml:mo>/</mml:mo><mml:mn>2</mml:mn></mml:mrow></mml:mrow></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> and O<mml:math id="E4" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mn>3</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math>, respectively. A 2-approximation of the quadrant merging problem is proposed. The proposed algorithm has time complexity <mml:math id="E5" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>O</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>α</mml:mi><mml:mn>2</mml:mn></mml:msup><mml:mi>T</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mi>n</mml:mi><mml:mo>)</mml:mo></mml:mrow><mml:mo>+</mml:mo><mml:msup><mml:mi>α</mml:mi><mml:mn>3</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> for any constant
α &gt; 1, where T(n) is the time complexity of the solution of the RDPT problem on one
quadrant. This result improves over the best previous quadrant merging solution which
has <mml:math id="E6" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>O</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mn>2</mml:mn></mml:msup><mml:mi>T</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mi>n</mml:mi><mml:mo>)</mml:mo></mml:mrow><mml:mo>+</mml:mo><mml:msup><mml:mi>n</mml:mi><mml:mn>3</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> time complexity.We test our algorithms on randomly uniform point sets and compare our heuristic
RDPT construction against a Minimum Cost Rectilinear Steiner (MRST) tree
approximation algorithm. Our results show that RDPTs are competitive with Steiner
trees in total wire-length when the number of terminals is less than 32. This result makes
RDPTs suitable for VLSI routing applications. We also compare our algorithm to the
Rao-Shor RDPT approximation algorithm obtaining improvements of up to 10% in
total wirelength. These comparisons show that the algorithms proposed herein produce
promising results.

Gustavo E. Téllez

Majid Sarrafzadeh

On Rectilinear Distance-Preserving Trees

In this paper a top-down methodology is presented for synthesizing clock distribution
networks based on application-dependent localized clock skew. The methodology is
divided into four phases: 1) determination of an optimal clock skew schedule for
improving circuit performance and reliability; 2) design of the topology of the clock tree
based on the circuit hierarchy and minimum clock path delays; 3) design of circuit
structures to implement the delay values associated with the branches of the clock tree;
and 4) design of the geometric layout of the clock distribution network. Algorithms to
determine an optimal clock skew schedule, the optimal clock delay to each register, the
network topology, and the buffer circuit dimensions are presented.The clock distribution network is implemented at the circuit level in CMOS
technology and a design strategy based on this technology is presented to implement the
individual branch delays. The minimum number of inverters required to implement the
branch delays is determined, while preserving the polarity of the clock signal. The clock
lines are transformed from distributed resistive-capacitive interconnect lines into purely
capacitive interconnect lines by partitioning the RC interconnect lines with inverting
repeaters. The inverters are specified by the geometric size of the transistors, the slope of
the ramp shaped input/output waveform, and the output load capacitance. The branch
delay model integrates an inverter delay model with an interconnect delay model.
Maximum errors of less than 2.5% for the delay of the clock paths and 4% for the clock
skew between any two registers belonging to the same global data path are obtained as
compared with SPICE Level-3.

José Luis Neves

Eby G. Friedman

Automated Synthesis of Skew-Based Clock Distribution Networks

With the increasing density of VLSI circuits, the interconnection wires are getting
packed even closer. This has increased the effect of interaction between these wires on
circuit performance and hence, the importance of controlling crosstalk. We consider the
gridded channel routing problem where, specifically, the channel has 3 routing layers in
the VHV configuration. Given a horizontal track assignment for the nets, we present an
optimal algorithm for minimizing the crosstalk between vertical wiring segments in the
channel by finding an optimal vertical layer assignment for them. We give an algorithm
that minimizes total crosstalk between vertical wires on the same V layer on adjacent
columns of the grid in O(ν logν) time using O(ν) memory, where the channel has ν
columns. We then extend this algorithm to consider crosstalk between wires in nonadjacent
columns and between wires on different layers. Finally, we show how our
algorithms can be extended to take crosstalk tolerance specifications for nets into
account.

Shashidhar Thakur

Kai-Yuan Chao

D. F. Wong

Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing

The synthesis of the power distribution network is an important problem in the layout
design of VLSI systems. In this paper we propose novel methods to solve the problem of
designing minimal area power distribution nets, while satisfying voltage drop and
electromigration constraints. We will see that our methods significantly improve upon
current techniques. We propose two novel greedy heuristics for power net design-one
based on bottom-up tree construction using greedy merging and the other based on top-down
linearly separable partitioning. We test the efficacy of our techniques on
benchmark instances. The areas required by our methods on typical instances are
significantly smaller than those obtained using previous methods.

Ashok Vittal

Malgorzata Marek-Sadowska

Power Distribution Synthesis for VLSI

In recent years there has been an extensive interest in clustering the modules of a
network so that the maximum delay from any primary input to any primary output is
minimized [8, 7, 6]. Clusters have a maximum capacity and modules may have different
implementations. All existing CAD frameworks initially select an implementation of
each module, and at a later stage they cluster the modules. We present an approach that
clusters the nodes, while considering their alternative implementations, so that we
further minimize the maximum delay after the clustering. Our approach is based on
optimal algorithms for restricted versions of this complex problem in circuit design, and
outperforms the conventional approach, which first obtains an implementation for each
circuit module without considering clustering and then, in a later step, performs
clustering.

Dimitrios Karayiannis

Spyros Tragoudas

Clustering Network Modules with Different Implementations for Delay Minimization

Inter-chip signaling latency and bandwidth can be key factors limiting the performance of large VLSI systems. We present a high performance, transmission line signaling scheme for point-to-point communications between VLSI components. In particular, we detail circuitry which allows a pad driver to sense the voltage level on the attached pad during signaling and adjust the drive impedance to match the external transmission line impedance. This allows clean, reflection-free signaling despite the wide range of variations common in IC device processing and interconnect fabrication. Further, we show how similar techniques can be used to adjust the arrival time of signals to allow high signaling bandwidth despite variations in interconnect delays.This scheme employed for high performance signaling is a specific embodiment of a more general technique. Conventional electronic systems must accommodate a range of system characteristics (e.g. delay, voltage, impedance). As a result, circuit designers traditionally build large operating margins into their circuits to guarantee proper operation across all possible ranges of these characteristics. These margins are generally
added at the expense of performance. The alternative scheme exemplified here is to sample these system characteristics in the device's final operating environment and use this feedback to tune system operation around the observed characteristics. This tuning operation reduces the range of characteristics the system must accommodate, allowing increased performance. We briefly contrast this sampled, system-level feedback with the
more conventional, fine-grained feedback employed on ICs (e.g. PLLs).

Andr&#xe9; Dehon

Thomas F. Knight

High Performance, Point-to-Point, Transmission Line Signaling

This paper presents a performance-oriented placement and routing tool for field-programmable
gate arrays. Using recursive geometric partitioning for simultaneous
placement and global routing, and a graph-based strategy for detailed routing, our tool
optimizes source-sink pathlengths, channel width and total wirelength. Our results
compare favorably with other FPGA layout tools, as measured by the maximum
channel width required to place and route several benchmarks.

Michael J. Alexander

James P. Cohoon

Joseph L. Ganley

Gabriel Robins

Placement and Routing for Performance-Oriented FPGA Layout

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