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VLSI Design
Volume 10 (1999), Issue 1, Pages 87-97
http://dx.doi.org/10.1155/1999/47230

Lower-Power and Min-Crosstalk Channel Routing for Deep-Submicron Layout Design

1Dept. of Elect. and Comp. Eng., Sungkyunkwan Univ., Suwon 440-746, Korea
2Fakultät Jür Math. und Informatik, Univ. Konstanz, Fach D 188, Konstanz D-78457, Germany

Received 7 September 1998; Accepted 20 November 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

S. H. Nam, J. D. Cho, and D. Wagner, “Lower-Power and Min-Crosstalk Channel Routing for Deep-Submicron Layout Design,” VLSI Design, vol. 10, no. 1, pp. 87-97, 1999. doi:10.1155/1999/47230