VLSI Design

VLSI Design / 1999 / Article
Special Issue

High Performance Bus-Based Architectures

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Open Access

Volume 9 |Article ID 75313 | 12 pages | https://doi.org/10.1155/1999/75313

Partitionable Bus-based String-matching Algorithm for Run-length Coded Strings With VLDCs

Received05 May 1997

Abstract

String matching (SM) problem is to find the occurrences of a pattern within a text. A vanable length don't care (VLDC) is a special symbol, not belonging to a finite alphabet ∑ but in ∑*. Each VLDC in the pattern can match any substring in the text. Given a run-length coded text of length 2n over ∑ and a run-length coded pattern of length 2m over ∑*, this paper first presents an O(1) time parallel SM algorithm for run-length coded strings with VLDCs on a reconfigurable mesh (RM) using O(nm) processors. Consider the hardware limitation in VLSI implementation. In order to be suitable for VLSI modular implementation, a partitionable parallel algorithm on the RM with limited processors is further presented. For N < n and M < m, the SM for run-length coded strings with VLDCs can be solved in O(X^Y^) time on the RM using O(NM)(= O((nm)/((X^Y^))) processors, where X^ = [(n – 1)/(N – 1)] and Y^ = [(m – 1)/(M – 1)].

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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