Table of Contents
VLSI Design
Volume 9, Issue 1, Pages 83-90

Reconfigurable Shift Switching Parallel Comparators

1Department of Computer Science, SUNY at Geneseo, Geneseo, NY 14454, USA
2Department of Computer Science, Old Dominion University, Norfolk, Va 23529, USA

Received 5 May 1997

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We present novel asynchronous VLSI comparator schemes which are based on recently proposed, reconfigurable shift switch logic and the traditional (precharged) CMOS domino logic. The schemes always produce a semaphore as a by-product of the process to indicate the end of domino process, which requires no additional delay and a minimal number of additional devices. For a large percentage of inputs the computations are much faster than traditional synchronous comparators due to the full utilization of the inherent speed of the circuits. Also the schemes are simple, area compact and stable.